Design Feature: August 3, 1995

Until recently, improvements in A/D (or data) converters' speed, accuracy, and resolution have had minimal impact on communications systems. Of course, converters are used extensively to digitize baseband information-bearing signals, which is a signal-format issue, not a fundamental architectural change. The classic Armstrong superhet design—with a local oscillator and mixer feeding an intermediate-frequency (IF) stage—so neatly separated and solved RF-tuning, selectivity, sensitivity, and demodulation problems that it's difficult to see where improvements can be made, except by integrating more of the functional blocks onto a single device.

All this is changing. Wide-bandwidth converters, coupled with appropriately characterized dynamic performance, enable a new converter architecture that moves the digital circuitry closer to the receiver front end and antenna. This technique (known as digital IF, bandpass sampling, IF sampling, or digital-to-baseband conversion) means that a much greater percentage of the receiver circuitry is implemented by purely digital circuitry. This, in turn, allows more of the receiver functional blocks to be put on fewer VLSI ICs, thus moving communications design toward a "three-chip" solution: an analog front end optimized for interfacing to the antenna or channel; an IF-to-baseband A/D converter, associated digital circuits, and DACs; and a software-driven processor that extracts and demodulates the desired signals, which can be either digital or analog.

At the same time, there are distinct limitations on what you can achieve with this architecture and what the cost in circuitry and software will be. The approach assumes that you know many of the parameters of the received baseband signal (fortunately, this is often the situation). If implemented improperly, your receiver can suffer from more than just "slight mistuning" and can produce useless strings of recovered signals and data.

Forget the old rules

A receiver's life isn't easy: It performs three major functions while encountering hostile real-world challenges. First, the receiver must tune (select) the desired carrier frequency (channel) and then amplify the weak tuned signal. Finally, it demodulates the tuned and amplified signal so that you can recover the baseband information. The receiver performs these functions despite received signal strengths at the antenna spanning and randomly varying over 100 dB of dynamic range (with typical signal values from 120 to 10 dBm), under difficult S/N-ratio conditions (0 to 50 dB), and with large adjacent signals making circuit linearity critical so that weak signals will not be obscured.

By mixing a broadband front-end signal with a local-oscillator (LO) signal, a traditional superhet design (Fig 1a) solves the problem of selecting a single carrier signal from within the broader spectrum. The LO is offset from the desired carrier by a fixed amount, such as 455 kHz or 10.7 MHz. The mixer produces sum and difference frequencies; the sum frequency is filtered out in the IF stage; and the fixed-frequency difference signal is further amplified, filtered, and passed to a baseband stage for demodulation (decoding).

Nothing in the superhet design restricts the type of modulation used (AM, FM, or PM) or the signal type (analog or digital) as long as you choose appropriate values for front-end, IF, and demodulation-stage parameters. One of the major virtues of the Armstrong superhet is that it allows you to set these circuit parameters independently of each other, with minimal interaction and, thus, to optimize each for the bandwidth, noise, modulation, and signal type at each stage.

Digital IF stages are not just implementations of the classic superhet using as much digital circuitry as possible (such as a digital LO). Instead, the digital IF stage uses a completely different approach to the problem (Fig 1b). Its core consists of an A/D converter that takes the RF or IF signal and deliberately undersamples it, thus bringing the information-bearing sidebands of the carrier down to baseband frequencies. (As in a double-conversion superhet, you first may have to down-convert the RF signal to a lower frequency when the carrier or first IF is too high for today's converters.) Computational circuits—usually a DSP—then extensively process this undersampled signal to extract the original baseband information. Although undersampling may seem to violate fundamental rules about Nyquist-rate sampling, it doesn't (see , "box" Nyquist, undersampling, and oversampling").

Potential performance-related advantages of digitally based receiver architectures parallel the virtues of digital circuitry in other signal-processing and signal-control applications. Your need to "tweak" circuitry to compensate for temperature drift and component tolerances is greatly reduced. You can use the same circuitry for different signals (bandwidths, modulation, encoding, channel spacing) because so much of the functionality is software- configurable. In an extreme case, you can employ a single converter and DSP to serve many signals at the same time—within the whole band of interest (see box, "The software radio: one converter for all").

You judge an A/D converter used for IF-to-baseband conversion using specifications that often differ from those used for converters intended for data acquisition. The repetitive characteristic of the input is one factor. Another important factor is that the bandwidth of the input signal to be digitized may be many times greater than the sampling rate—a situation that doesn't occur in conventional data-acquisition roles.

Begin your converter analysis with the traditional differential nonlinearity (DNL) and integral nonlinearity (INL) measures. DNL indicates variations of code width from the ideal 1-LSB value; increases in DNL, which generally occur with higher input frequencies, appear as an increase in quantization noise and a rise in the converter's noise floor. (Theoretically, rms quantization noise for an ideal converter equals the value of a LSB divided by [sqareroot]12.)

INL measures center deviations of each converter code from the ideal, straight-line transfer function (as drawn through the transfer-function endpoints or as a best-fit straight line through the data points). Such deviations, or bends in the straight-line transfer function, result in the converter's generating harmonics and spurious frequencies that were not present in the original waveform being digitized.

The type and magnitude of these new signal components are better described by frequency-domain specifications (Fig 2), including an alphabet soup of SINAD (signal-to-noise and distortion), S/N ratio, SFDR (spurious-free dynamic range), and ENOB (effective number of bits), along with the more familiar THD (total harmonic distortion) and IMD (intermodulation distortion). Vendors test their converters by feeding a pure tone (or tones) to the converter and analyzing the resulting stream of data with FFT and other analyses. Both the input frequency and the sampling rate should be specified, of course.

SNR is classically based on the ratio of the rms signal value to the rms noise value, where the noise does not include the fundamental frequency or the first five harmonics:

Because the S/N ratio doesn't include the major harmonics, it is not truly indicative of the converter's dynamic range. For that measure, you'll need to use SINAD and ENOB. What SNR does tell you, however, is how close the actual noise floor is to the theoretical value.

SINAD uses the same formula as S/N ratio but replaces the rms noise-voltage value with a voltage that includes all spectral components below the Nyquist frequency, except for fundamental and dc. Typical SINAD values for converters range from 40 to 60 dB, usually a few decibels less than the corresponding S/N ratio.

ENOB, SFDR are critical

Using SINAD, you can calculate an overall indication of the converter's accuracy and dynamic performance, or ENOB, using

The closer the ENOB is to the converter's nominal resolution, the better the device's dynamic performance. ENOB values are typically 1 to 2 bits below nominal resolution. ENOB decreases with increasing frequency, so make sure the frequency you'll be using is covered by the vendor's specification. Some applications require ENOB specs of 10 to 11 bits; others need only 6 to 7 bits.

Note that this formula comprises two terms. The second term recognizes that ENOB will increase if the applied signal amplitude is less than the converter's full-scale span. Although it is a relatively small factor compared with the first term (unless the applied signal is much smaller than full scale), check to see if the SINAD conditions are comparable when looking at converters from different vendors.

Another indication of the converter's nonlinearity is its SFDR. SFDR is the ratio in dBc (decibels with respect to the carrier value) of the fundamental's rms amplitude to the next largest spur (spectral component) when the input is a single tone. Although this spur is often related to a harmonic of the fundamental, it doesn't have to be. For example, the converter clock, which is not directly related to the input signal frequency, may be coupling in to the converter due to the circuit layout and crosstalk. SFDR values range from 50 to 80 dB, typically, depending on specific converter and test conditions.

Along with SFDR, THD quantifies the converter's nonlinearity using the ratio (in dBc) of the rms noise amplitude to the rms signal (single-tone) amplitude, where the noise is measured by summing the first few harmonic components. Most tests sum through the first five components for completeness, because the second and third harmonics contain most of the distortion power.

Multiple signals, multiple tones

A communication system normally must deal with a signal spectrum that contains more than just a single component at a time (which, after all, would convey little information). This puts a premium on device linearity. The converter's IMD is tested with two nonharmonically related tones of approximately equal amplitude. When there is any nonlinearity in the signal path, these tones (at frequencies f₁ and f₂ generate harmonic-distortion terms at integer multiples of f₁ and f₂ plus intermodulation (IM) tones at mf₁+nf₂ (where n and m are any integers).

IMD is calculated using the ratio of the rms sum of the first IM terms to the rms value of the sum of the two applied tones. One issue to consider is the number of IM terms to be included. Most vendors include through the fifth order, where the order is defined as |n|+|m|, since second- and third-order terms usually dominate. Available IMD specs range from 70 to 90 dB.

You probably will be most concerned with the third-order term, due to the "near-far" problem. When two relatively strong adjacent signals occur at f₁and f₂, they can produce third-order terms at 2f₁- f₂ and f₁-2f₂, which fall close to either f₁ or f₂, thus masking a relatively weak in-band adjacent signal. To better replicate real-world conditions, some vendors are also quantifying IMD performance with more than two simultaneous tones.

Sampling-time-aperture issues are also critical. Ironically, aperture delay—the lag between the ideal "requested" sampling instant and the actual sampling time—may be an important data-acquisition parameter, but it is not a factor in communications applications because the sampling action is repetitive. What does matter is aperture jitter, the uncertainty and variation in sampling time caused by internal converter noise and clock jitter. This jitter noise phase-modulates the sampling time, limiting the maximum dV/dt input slew rate—and, hence, maximum frequency—that will have a dV error less than ½ LSB:

where t_AJ is rms aperture jitter and n is the nominal converter resolution. The effect of timing jitter on SNR is

Timing jitter reduces the effective S/N ratio you can achieve, raising the noise floor that the basic S/N ratio equation indicates:

Note that this specification assumes you are providing a jitter-free conversion clock to the converter or its S/H circuit. Your clock-source quality and careful signal routing (to minimize noise and crosstalk) are critical. For example, just 20 psec of rms jitter on a 12-bit converter with a 1-MHz input reduces S/N ratio by 1.5 dB. If your analysis shows that applied clock jitter may be a significant error factor, you should identify and reduce sources of jitter (see Ref 5).

Consider using an external S/H circuit to increase both SFDR and ENOB, even for converters that have an internal S/H. But be prepared to work out the two-chip error budget. Make sure the S/H you select offers low distortion in its hold mode at the frequency of your input signal. Note that many S/Hs are specified for distortion when tracking, and the corresponding hold-mode figures may be harder to find.

Driving the A/D converter properly is critical (see Ref 6). Most sources have a 50[lower case Omega] impedance; any mismatch or distortion in your signal path will degrade achievable performance.

Even if all the converter specs are sufficient, you still have to examine the device and circuit bandwidth. Full-power bandwidth is the critical parameter for your digital-IF-to-baseband technique to work properly. Although there are many definitions of bandwidth, the most common uses the traditional 3-dB point, where the converter's reconstructed input is 3 dB below its low-frequency value.

Normally, you don't want to operate near this 3-dB point, however. By operating the converter in the relatively flat zone (well below the 3-dB point), you'll minimize inadvertent gain-and-phase distortion. Also, consider the limitations of any input buffers or layout between your analog input signal and the converter's input.

Be sure that the vendor specifies input bandwidth using a full-scale signal (several volts) rather than a small-signal input (10s of millivolts). Small-signal inputs can yield especially favorable results; they don't stress the converter fully, because they don't cause slew-rate limitations or other large-signal effects. Full-scale test inputs that are 0.5 dB below the converter's maximum input range are most commonly used.

Specs and more specs

Dynamic specs are essential for determining a suitable A/D converter. There are some ways in which available component specs can be misleading. When the sampling frequency is coherent with respect to the input-signal frequency, the input-signal energy falls into one FFT bin. However, when the sampling isn't coherent—the ratio between signal and sampling frequencies is not the ratio of two integers—the waveform samples will smear into FFT bins around the fundamental.

To compensate, the vendor can establish a window around the fundamental bin. However, this option also reduces or eliminates noise energy that happens to be in these bins, thus affecting subsequent computations and improving some specs.

When you start evaluating potential converters (see Table 1 ), don't be surprised if some of the converters have video-application specs. Many communications converters were originally intended for video digitization, and many of the performance attributes and specifications are similar.

If you're deciding whether to pursue a digital-to-baseband approach, consider component cost, potential benefits, and complexity. The digital method is more than just a theory: It's being used successfully in Global System for Mobile (GSM) cellular phones and its US equivalents, as well as in cellular base stations, which demodulate a variety of input formats such as US digital cellular, conventional Advanced Mobile Phone Service analog cellular, and others. These applications represent opposites in system flexibility: The phone unit is a single-format device, and the base station is a multiple-format system.

For either approach, you'll need an RF stage (and AGC) to capture the weak antenna signal, and you'll probably need a first conversion stage to bring the RF carrier down to a more manageable IF frequency. For getting the IF down to baseband, consider that a digital solution may be more expensive than an analog one, even with today's lower cost converters and DSPs. Existing analog techniques have been in place for so long that many low-cost and optimized mixers, gain-control blocks, IF filters, and demodulators are available.

Try to quantify the benefits and determine exactly what performance or implementation advantage each approach provides. Are you seeking improved bit-error rate (BER), audio fidelity, adaptability in performance, VLSI integration, or flexibility to handle different types of inputs? If you don't need the flexibility, for example, the digital solution may be solving a problem you don't have. Perhaps you can achieve your goals by circuit and component optimization with a conventional superhet.

Finally, consider the complexity and unknowns of your received signal and the signal uncertainties introduced by the medium you are using, whether it's air, copper cable, or optical fiber. Your received-signal-recovery challenge is divided into three categories of increasing difficulty ( Table 2and Ref 1): signal detection (simply determining signal presence or absence), signal estimation (determining a signal value at one isolated time only), and continuous signal estimation (determining the value of a continuously varying analog signal). Any receiver design must be robust enough to handle the unexpected, such as noise bursts, carrier fading and dropout, multipath signals, and similar woes, by degrading as gracefully as possible rather than have sudden increases in BER or loss of analog performance.

For all three categories of signal difficulty, there is a hierarchy of challenge for the receiver. The challenge increases the less you know about the incoming signal. The simplest category is the relatively known signal-in-noise, which is followed by the signal-with-unknown-parameters-in-noise. Most difficult is the random-signal-in-noise.

As you move from the simplest case of signal detection for a known signal toward the most difficult case of continuous estimation of a random signal, the algorithms you need to embed in the DSP become more complex to develop and more time-consuming to execute. Implementing these algorithms efficiently is important because virtually all communication algorithms must execute in an isochronous mode, with the signal processed fast enough so that no incoming signals (or sample points) are missed.

Finally, consider where you will obtain the code to drive the DSP. If you have to develop the code yourself, it may be hard to determine how long it will take to implement, debug, and field-test your coded algorithms—and estimate the required memory, as well. Fortunately, for some standard communication applications such as GSM and digital cellular, DSP vendors and independent third parties offer code modules that are tested and benchmarked using specific vectors and patterns established by the standard. This, of course, greatly reduces the coding you have to do and the uncertainties you face.

References

1. Van Trees, H L, Detection, Estimation, and Modulation Theory, John Wiley and Sons, 1968.
2. Mitola, J, "The Software Radio Architecture," IEEE Communications Magazine, May 1995.
3. Ramirez, Robert, The FFT: Fundamentals and Concepts, Prentice-Hall, 1985.
4. "Dynamic Testing of A to D Converters," Hewlett-Packard Product Note 5180A-2.
5. Schweber, Bill, "Delivering the high-speed clock: it's not easy to be on time," EDN, July 6, 1995, pg 32.
6. Swager, Anne, "Evolving ADCs demand more from drive amplifiers," EDN, Sept 29, 1994, pg 53.