Design Ideas: October 12, 1995
The programmable data-acquisition system in Fig 1 can take 333k samples/sec using a 3-µsec sampling ADC, IC3. Multiplexer IC1 and programmable gain amplifier (PGA) IC2 provide four truly differential channels and four decade gains of 1, 10, 100, and 1000. These features allow the circuit to handle low-signal sensors without additional conditioning circuitry. The circuit does not require an S/H amplifier due to the ADC's sampling structure. If you want to handle noisy and high-speed signals, you may need to add an antialiasing filter in front of the ADC.
The heart of the system is a 4x4 register file, IC5, which essentially controls the multiplexer and PGA and allows you to program these ICs up to four samples deep. You can asynchronously program IC5 on the fly, regardless of the conversion rate and clock.
The clock signal controls the circuit and has a maximum frequency of 333 kHz. The rising edge of the clock drives sequence counter IC4, which then selects a register inside IC5. The output of IC5 sets the multiplexer's channel number and the PGA's gain. This feature allows the circuit to start signal acquisition, even during a previous conversion, because the ADC has already stored the previous signal level. The falling edge of the clock initiates a conversion and latches the channel number and gain into IC6. The rising edge of the busy signal latches 16-bit data from IC3 and IC6 into a RAM or FIFO buffer. The 2 MSBs show channel number, the next 2 bits show gain, and the remaining 12 bits represent ADC data.
By varying clock, you can vary the circuit's sampling rate. If you need to handle more channels and PGA gains, you can parallel 4x4 registers to provide a longer control word. To increase the programmable sequence, you can wire-AND these register files. If you want to have long channel numbers and long gain-programming sequences, you can use dual-port RAM instead of register files.