Out in Front: November 9, 1995

Two recent announcements have demonstrated the electronic-design-automation industry’s increasing recognition that hardware/software co-development is becoming a bottleneck to embedded-core-chip design. First, Mentor Graphics and Microtec Research recently announced a merger in which Microtec will become a business unit of Mentor Graphics. The combination of Mentor Graphics’ hardware-design tools and Microtec’s software-development tools and real-time operating-system products provide a basis for tools and design methodologies that address hardware/software co-design throughout the design of an embedded system. Although the companies won’t announce specific products until 1996, the two companies have defined the dynamic-design-integration (DDI) process. DDI will include tools for coverification, coanalysis, and co-design of chips and PC boards combining hardware and embedded software.

Second, addressing hardware/software co-development specifically for DSP chips is Synopsys’ latest version of the COSSAP DSP-design tool suite. COSSAP 7.0 lets a single source specification generate the hardware specification as a hardware-description language (HDL) and DSP software as C code. You graphically create the initial system, using predefined library elements and user-defined blocks. There are more than 900 library blocks, including behavioral representations of FIR and IIR filters and various coding and modulation communication elements. After you capture the design, the COSSAP stream-driven simulator lets you make design modifications to your design.

From the optimized design specification, you develop behavioral VHDL code or register-transfer-level (RTL) code, either as Verilog or VHDL. At this point, you can explore architectural alternatives in Synopsys’ behavioral compiler to optimize your design hardware for parameters such as area, speed, resource sharing, and latency. You can also synthesize a gate-level representation of the system’s hardware to implement either as an ASIC- or a field-programmable gate-array-based design. COSSAP provides an interface to let you simulate behavioral, RTL, and gate-level representations of your design.

You use the same system specification and COSSAP’s DSP code generator to generate C code for targeted DSP processors, including ones from AT&T, the DSP Group, and Texas Instruments. You can get DSP development kits targeted toward different DSP cores for hardware/software cosimulation. During code generation, you can explore program architectures to meet scheduling, pipelining, and memory-allocation specifications.

COSSAP 7.0 will be available in January at a price starting at $40,000. You will probably also want a hardware-implementation package, which includes COSSAP 7.0, the HDL code generator, and libraries. The package costs $66,100. A software-implementation kit, which also includes COSSAP 7.0, costs $50,000. The newest DSP developer kit, for DSP Group’s Oak core, sells for $7500.
—by Jim Lipman

Mentor Graphics, Wilsonville, OR. (503) 685-7000.

Microtec Research, Santa Clara, CA. (408) 980-1300.

Synopsys, Mountain View, CA. (415) 962-5000.