Out in Front: November 9, 1995
Atmel’s 44-pin ATF1500 flash-based complex PLD (CPLD) connects every input and feedback to every product term of each of 32 macrocells. This type of architecture yields 100% connectivity and avoids the pitfalls of segmented architectures, such as partially populated switch traces. This architecture also eliminates pin-assignment changes if a design needs modification.
The ATF1500, pin-compatible with Altera’s 7032, contains 1500 equivalent user-configurable logic gates and has a 7.5-nsec maximum propagation delay (Tpd). These CPLDs support individual output-enable control of each pin via a product-term output-enable control. Furthermore, the I/O pins can latch the last signal driven, eliminating the need for external pullups.
Designers using this device can trade off lower output noise for output speed; output-slew-rate control allows individual control of each output pin. The device comes in 5V, and Atmel plans to add 2.7V versions soon. The ATF1500 has a sleep-mode option that lowers current consumption to 10 µA. Available in PLCC and TQFP, the ATF1500 sells for $5.76 (100).
Atmel is also offering new development support for the entire CPLD product line. The Windows-based Atmel Synario, which Data I/O makes and Atmel sells, sells for approximately $1000. Synario performs schematic capture and functional simulation and includes fitters for all of Atmel’s parts. You can also purchase an optional Verilog timing simulator and VHDL synthesizer.
—by Markus Levy
Atmel Corp, San Jose, CA. (408) 441-0311.