Out in Front: November 9, 1995

The Cypress Ultra3800 family of field-programmable gate arrays (FPGAs) offers high performance and as many as 20,000 usable gates. The 3.3 and 5V devices employ an antifuse programming structure, which reduces capacitance to offer data-path performance greater than 200 MHz and loadable counter frequencies greater than 185 MHz.

A VL2.7 triple-layer metal allows the interconnection structure to reside above the logic layer, which reduces die size by approximately 50%. The FPGAs offer JTAG (Joint Test Action Group) compatibility for JTAG-system test and diagnostics, and they comply with the PCI specification. Seven densities are available, ranging from 3000 to 20,000 usable gates. The devices come in PLCC, TQFP, PQFP, and ball-grid-array packages with 84 to 352 I/O pins.

A logic cell with a wide fan-in lets you implement complex functions at high speeds. You can fragment the logic cell into as many as five unique functions; this fragmentation emulates a sea-of-gates architecture. The ViaLink elements reside between the second and third layers of metal, which leaves the first level for logic. The ViaLink programming elements are one-seventh the size of SRAM-based elements; as a result, the ViaLink elements have less resistance and capacitance than do SRAM-based devices.

The 7000-gate CY7C3807 will be available in the first quarter of 1996; prices will start a $69.50 (100). Cypress plans to roll out higher density family members later in the year, and the 20,000-gate CY7C3820 device will become available in the third quarter.
—by John Gallant

Cypress Semiconductor Corp, San Jose, CA. (408) 943-2000.