Out in Front: November 23, 1995
The 26th International Test Conference, which convened in Washington, DC, a few weeks ago, took as its theme "Driving down the cost of test." Attendance at ITC increased by 22% from last year, reflecting the current boom in the automatic-test-equipment (ATE) industry. Although many ideas emerged for cutting test cost, it's safe to say that no magic bullet offered a sudden, dramatic cost reduction. The closest thing was probably the recognition that built-in self-test (BIST) technology's time has finally arrived.
One of the factors driving BIST's elevated status is IC and ATE vendors' awareness that, absent some new approach, in an era of ICs that contain many tens of millions of gates, the industry is not far from needing testers that cost tens of millions of dollars. Such testers not only would impose financial burdens that IC companies are unable -- or at least unwilling -- to bear, but also would be so complex that their MTBF would be unacceptably short.
BIST proponents, such as AT&T Design Automation and LogicVision, insist that BIST holds the key to much simpler and less expensive IC testers. LogicVision held a press conference at which representatives of several prominent companies endorsed the use of LogicVision's BIST tools. According to LogicVision, the event marked BIST's coming of age.
Adding BIST features modestly increases the size -- and, hence, the cost -- of IC dice. The ITC keynote address made clear that, despite demanding lower tester cost, important segments of the IC industry are unwilling to accept increases in die size. To make this case, Intel executive Ken Thompson, who prefaced his remarks by saying that he was speaking for himself and not for his employer, invoked statistics that some listeners found incomprehensible. For example, Thompson used a 15% area penalty for testability features, at least three to five times the actual penalty on complex chips. Then, Thompson stated that, if chip area grew by 15%, the number of good dice per wafer would decline by 32%. Although the number of good dice does decline faster than chip area increases, Thompson did not explain why the ratio was so high.
Supporting Thompson's position and notwithstanding BIST proponents' assertion that the most pervasive BIST technology is memory BIST, suppliers of large memory test systems say they see only increasing demand for their systems. These companies see no indication that their target market -- manufacturers of large memory ICs -- will accept even modest increases in chip area to reduce tester cost. (Memory BIST's main area of penetration appears to be in embedded memory structures in ASICs. The economics of ASIC and memory-chip manufacture differ radically.) One company that showed a major new memory test system is Megatest. This was probably Megatest's last ITC as an independent company; a merger with Teradyne is in the works. Megatest says that little overlap exists between its new 100-MHz Pegasus systems (from $850,000), which test 64 bytewide devices simultaneously, and Teradyne's J990 series. The merged company will position the Pegasus systems above the less expensive, lower speed J990s, which test fewer devices at once.
A subplot to the BIST story is the significance of IEEE-1149.1 boundary scan, a technology that is causing a quiet revolution. The chances are that few EEs who design ASICs and digital pc boards would say that the IEEE-1149.1 testability standard has had much of an impact on them. Yet, estimates of the dollar value of parts that include IEEE-1149.1 features run as high as 40% of the total value of digital ICs shipped. Not all companies that use these ICs are taking advantage of the boundary-scan features, but many are, including Intel's market-share-leading PC-motherboard business. The use of IEEE-1149.1 in motherboard testing is the most likely reason for Intel's implementation of the testability standard in three generations of X86 mPs. The company must be leveraging IEEE-1149.1 to level the playing field with offshore board suppliers, few of which take advantage of boundary scan. Unlike IC manufacture, board manufacture is a business with a low cost of entry. Therefore, Intel would not want to say much about a technology that underlies its competitive edge.
IEEE-1149.1 is useful for much more than continuity testing on pc boards, however. The IEEE-1149.1 test-access port (TAP) and TAP controller have become the de facto industry standard for accessing a chip's BIST features.
-- by Dan Strassberg
AT&T Design Auto-mation, Allentown, PA. (800) 875-6590.
LogicVision, San Jose, CA. (408) 453-0146.
Megatest Corp, San Jose, CA. (408) 437-9700.
Teradyne Inc, Agoura Hills, CA. (818) 991-2900.