Design Ideas: March 28, 1996
If you've tried to design a video-overlay board that works with super-video-graphics-adapter (SVGA) graphics through a feature connector, you've probably noticed that the frequency of the supplied clock signal is not always equal to the pixel-clock frequency. In high-color modes (32,000, 64,000, and 16 million colors), the clock usually runs at 2 or 3× the pixel frequency. You can restore the pixel clock by using a simple programmable divider, as opposed to the more complex PLL circuit used in many video-overlay boards. Figure 1 shows the divider circuit.
The circuit works as a 1-to-1, 1-to-2, or 1-to-3 divider and has some desirable attributes: No delays are inherent in the feedback path, so the divider can operate to the maximum frequency the flip-flops allow. You can also synchronize the divider if necessary. Finally, you can switch the output clock off. You set the divider ratio according to Table 1. In 1-to-1 mode, the input clock appears at the PR input of IC2B. Because the CL remains in a constant-zero state, the clock propagates to the CLKR output. The circuit can operate above 100 MHz in the divider modes. In direct (1-to-1) mode, the bandwidth is slightly limited by the nonstandard usage of the set/clear inputs of the second flip-flop. Synchronization is optional; if required, you can implement synchronization by using short (single-clock-width) pulses on the RSTIN line. Synchronization can be useful for imposing a known phase of the restored clock at the start of each scan line. 
Figure 2 gives a timing diagram for the circuit, with examples of RSTIN usage. The circuit can function as a general-purpose programmable divider.
| Table—Programmable divider ratio codes | |
|---|---|
| SET[2..0] | Function |
| 000 | Output=0 |
| 001 | 1-to-1 (direct) |
| 010 | 1-to-2 divider |
| 110 | 1-to-3 divider |