Figure 1 shows a voltage-to-frequency (V/F) converter that produces a 0- to 10-kHz output for an input range of 0 to 5V. Linearity of the converter is 0.02%, and gain drift is 60 ppm/8C. The maximum current consumption is only 26 µA, 100 times lower than currently available units. To understand the circuit's operation, assume that the voltage at IC₁'s negative input is lower than the voltage at its positive input (IC₂'s output is low). The input difference results in a positive-going ramp at IC₁'s input (Figure 2, trace A).

IC₁'s output is high, allowing current to flow from the emitter of Q₁, through IC₁'s output stage, to the 100-pF capacitor. The 2.2-µF capacitor provides high-frequency bypassing, maintaining low impedance at the emitter of Q₁. The diode-connected transistor, Q₆, provides a path to ground. The voltage to which the 100-pF capacitor charges is a function of Q₁'s emitter voltage and the drop in Q₆. IC₁'s purely ohmic CMOS output contributes no voltage error. When the ramp at IC₁'s negative input goes high enough, IC₁'s output switches low (trace B) and the inverter switches high (trace C).

The switching action pulls current from IC₁'s negative-input capacitor via the Q₅ route (trace D). This current removal resets IC₁'s negative-input ramp to a potential slightly below ground. The 50-pF capacitor furnishes positive ac feedback to IC₁'s positive input (trace E), ensuring that IC₁'s output remains negative long enough for a complete discharge of the 100-pF capacitor. The Schottky diode prevents IC₁'s positive input from going outside its negative common-mode limit. When the feedback from the 50-pF capacitor decays, IC₁ again switches high and the entire cycle repeats. The oscillation frequency depends directly on the input-voltage-derived current.

It's necessary to carefully control Q₁'s emitter voltage to obtain low drift. Q₃ and Q₄ temperature-compensate Q₅ and Q₆, and Q₂ compensates the V_BE drop of Q₁. The three LT1004s provide the voltage reference, and the LM334 current source provides 12-µA bias to the reference stack. The current drive provides good supply immunity (better than 40 ppm/V). The current drive also aids the circuit's temperature coefficient by using its own 0.3%/°C temperature coefficient to slightly temperature-modulate the voltage drop in the Q₂/Q₃/Q₄ trio. This correction's sign and magnitude directly oppose the -120-ppm/°C drift of the 100-pF polystyrene capacitor.

The isolated drive from Q₈ to the CMOS inverter prevents output loading from influencing IC₁'s operating point. The Q₁ emitter follower efficiently delivers charge to the 100-pF capacitor. Both the base and collector current go to the capacitor. This capacitor, as small as accuracy permits, draws only small transient currents during its charge and discharge cycles. The 50-pF/100-k(ohm) positive-feedback combination draws insignificantly small switching currents. Figure 3, a plot of supply current vs operating frequency, reflects the low-power design.

At zero frequency, the comparator's quiescent current and the 12-µA reference-stack bias account for all current drain; no other paths exist for loss. As the frequency scales up, the charge-discharge cycle of the 100-pF capacitor introduces the 1.1-µA/kHz increase shown in Figure 3. A lower value capacitor would cut power, but the effects of stray capacitance and charge imbalance would introduce accuracy errors. Circuit start-up or overdrive can cause the circuit's ac-coupled feedback to latch. If latching occurs, IC₁'s output goes low. IC₂, detecting the low transition via the inverters and the 2.7-M(ohm)/0.1-µF lag network, goes high. This transition lifts IC₁'s positive input and grounds the negative input via Q₇, thereby initiating normal circuit activity.

To calibrate the circuit, apply 50 mV and select the indicated resistor at IC₁'s positive input to produce a 100-Hz output. Complete the calibration by applying 5V and trimming the output potentiometer to yield a 10-kHz output. (DI #1881)