Design Features

Embedded memory enhances programmable logic
for complex, compact designs

Rick Nelson, Contributing Editor

The growing densities of PLDs are making the chips suitable for increasingly complex designs. Those designs, in turn, require high-performance scratchpad RAM for temporary storage of data that passes through the logic circuitry that the chips implement. Vendors are responding with devices that incorporate memory as well as logic gates. 

  PLDs ranging from complex, cell-based implementations to FPGAs are no longer merely implementing a few TTL chips' worth of glue logic. Instead, as gate densities move toward 100,000 gates per device and beyond, PLDs are becoming subsystems on a chip. Recognizing this trend, PLD vendors are increasingly incorporating the memory capacity that such subsystems demand.

  The goals are increased performance and reduced chip count. A single chip incorporating logic and memory takes up less board real estate than a separate PLD plus RAM chip would. Further, the embedded approach eliminates board-level routing complexities and the attendant delays in chip-to-chip data transfers.

  "People buy our devices not for a particular RAM capacity, but because they want a one-chip solution," says Sandeep Vij, director of FPGA marketing at Xilinx.

  That's not to say that a PLD with embedded memory is a panacea. "If the majority of the silicon on a programmable-logic chip is devoted to memory functions, your device is in danger of becoming primarily a memory device and of having to compete with memory pricing," says Stan Kopec, marketing director at Lattice Semiconductor. "The memory content of a programmable device must be less than half—let's say one-third—of the silicon area, to avoid this situation."

  But numerous applications, ranging from data communications and telecommunications to PC add-ons, do fall within Kopec's recommended embedded-memory-to-logic ratio. "Any system requiring some fast buffer memory for data and some custom logic is a suitable application, he says. Bob Beachler, strategic marketing manager at Altera, concurs that embedded-LD applications are diverse.

  "We do 50% of our overall PLD business in telecomm and datacomm, including cellular base stations and PBX switches, and 17% in computers and peripherals, with applications like industrial control taking up the rest," says Beachler. He expects application distribution to stay the same for the Flex 10K, Altera's pioneering family of embedded-array PLDs.

  For such applications, the case for embedded PLDs is clear. Less clear is determining which of the available configurations is best for your application. Table 1provides an overview of gate count, memory capacity, speed, and other specs. It's difficult to make design decisions on such specs, however, because of the varied ways in which vendors implement the logic and memory functions. For any implementation, performance can depend heavily on the accumulation of microparameters, such as logic delay and address setup time of individual logic cells or memory blocks within a device. Lattice's Kopec elaborates on this point.

  "All times we quote for our CPLDs are pin-to-pin worst case, including worst-case programmable-interconnect delays," he says. "FPGA vendors typically quote internal block delays without programmable-interconnect and I/O-buffer delays." Kopec claims this omission is due to the unpredictability of FPGA interconnection, varying from 10 to 30 nsec. You must add worst-case programmable-interconnect and buffer delays to an FPGA's quoted specs, he says, to get real, in-system performance. Lattice's CPLDs offer worst-case interconnect delays of 3 nsec across the entire chip, he says.

  Naturally, vendors publish specs, such as those in Table 1, that reflect their devices' performance in the best possible light. Because your application requirements seldom precisely match a vendor's test model, you must carefully consider all of the available embedded-PLD configurations to avoid incurring subtle penalties in performance, real estate, and cost.

The embedded-PLD gamut

  The range of configurations begins with the tabula rasa of Xilinx's XC4000 devices at one extreme (Figure 1). On the XC4000's "blank slate" of uncommitted logic blocks, you design your choice of synchronous or asynchronous, single- or dual-port memory, and logic functions, distributing each freely throughout the chip.

  At the other extreme is the WaferScale Integration Inc (WSI) PSD family (Figure 2). In addition to programmable logic, PSD devices include dedicated functions, such as interrupt controllers, counter/timers, EPROM, and RAM, carved in stone. The PSD devices are less PLDs with embedded memory than dedicated chips with some embedded field-programmable logic.

  In fact, the WSI parts extend the capabilities of standard, off-the-shelf microcontrollers from such companies as Intel (Folsom, CA), Motorola (Austin, TX), and Zilog (Campbell, CA). The goal is to let you add a $10 PSD part to an overburdened $3 microcontroller, instead of replacing the $3 microcontroller with a $30 or even $100 one. However, the WSI approach is anathema to traditional PLD manufacturers.

  Says Altera's Beachler, "I could put a PCI core on a PLD, but then I could sell it only to the PCI bus people, and that's never been the idea for programmable logic." It doesn't make marketing sense for his company to pursue a niche with only 100 customers, he says: "The goal is a broad customer base, not a narrow one. Within the past 12 months we've shipped to almost 13,000 customers."

  The Xilinx approach optimizes design flexibility; WSI aims at optimum price/performance for very specific applications. Altera's PLD architecture stakes out a position between these extremes, as do technologies from companies including Actel, Lattice Semiconductor, and Lucent Technologies.

  Yet another approach comes from Chip Express (San Jose, CA). Its laser-programmable gate arrays (LPGAs) aren't user-programmable, so they don't qualify as FPGAs. Nevertheless, the company can offer a one-day turnaround on prototypes, making the devices nearly competitive with field-programmable devices with respect to product-development cycle times. If you need gate counts beyond what FPGAs offer or if you anticipate extremely high production volumes, LPGAs might be your best choice. The company's CX2000 LPGAs provide 30,000 to 200,000 usable gates and as much as 128 kbits of 200-MHz SRAM, configurable as FIFO, single-port, or dual-port memory. An 80,000-gate device costs about $20 in very high volumes; comparable PLDs generally cost more than $100 in production quantities.

  All of these companies are attempting to balance design flexibility and speed for logic and memory configurations, and each vendor counts on its approach meeting most of your application needs.

Performance vs flexibility

  The trade-offs that vendors juggle stem from two inescapable factors. On the one hand, a relatively large, contiguous block of dedicated RAM takes up less silicon and achieves better performance than implementing the same bit-storage capacity in a general-purpose sea of gates. On the other hand, a dedicated memory block is less efficient than distributed logic for applications whose memory needs don't closely match the dedicated block's capacity and organization.

  Secondary factors come into play as well. Proponents of dedicated embedded RAM make several arguments. For example, they often claim that designers can use any surplus RAM as a look-up table, thus converting the RAM to logic in a way that mirrors the flexibility of distributed-logic architectures.

  Further, Warren Miller, Actel's director of product planning and applications, echoes a concern of Lattice's Kopec: a problem with distributed memory, he says, is predictability.

  "You can't easily predict the performance of the memory, because the signals going to memory can be spread across the device," says Miller. His company's A3200DX devices include eight to 15 optimized 32×8-bit, dual-port RAM blocks that operate at 100 MHz. These blocks find use as scratchpads, register banks, microcoded state machines, line buffers, cache RAM, status registers, multiprocessing mailboxes, and address pointers for data-structure linked lists in applications ranging from pattern recognition to convolution.

  Actel's PLD memory boasts the highest speeds of the vendors of field-programmable PLDs that this article covers. However, for relatively small memory-block requirements, memory implementations in distributed logic can be faster than some vendors' block-memory implementations, according to Vij at Xilinx.

  "If you need single- or dual-port memory up to 32×32 bits, the XC4000 series is faster" than some competitors' PLDs with blocks of single- and dual-port RAM, he says. "As you move to larger memory, you are more likely to use dual-port RAM, so we optimized the 4000 Series for the dual-port configuration." Vij cites a 12-nsec access time for an XC4000 8×32-bit, dual-port RAM as an example of XC4000 performance. He concedes that XC4000 memory performance gradually declines as memory blocks get larger, and block-memory architectures suffer stepwise speed reductions when memory demands increase to levels at which you must cascade remote blocks.

  Vij takes exception to claims that unused portions of memory blocks can adequately implement logic functions. "With a block structure, if you don't use RAM, it's wasted. People may claim that you can put logic functions there, and a few, like multipliers, will fit, but most simply will not. With distributed logic, you can trade off as necessary without sacrificing logic performance."

Logic units, embedded arrays

  Xilinx based its XC4000EX FPGAs on configurable logic blocks (CLBs) distributed uniformly throughout the chip. You can combine these building blocks to implement a variety of logic and memory functions. You can use 72 of them, for example, to build a 256×8-bit, single-port RAM or 48 to build a 32×16-bit, simultaneous-read/write FIFO buffer. On the logic side, you can use one CLB to implement, for instance, a 9-bit parity checker or 400 to implement a 55-MHz, 8-bit, 16-tap parallel FIR filter.

  Lucent Technologies takes a similar approach with its ORCA (Optimized Reconfigurable Cell Array) devices (Figure 3). Lucent's version of the CLB is the programmable function unit (PFU). Each PFU contains four 16-bit look-up tables (LUTs) and four flip-flops. The LUTs can operate in any of three modes. In combinatorial mode, they can realize any four-, five-, or six-input logic functions. Ripple mode adds a high-speed carry capability for implementing arithmetic functions, and in memory mode, the LUTs can implement 16×4-bit, single-port or 16×2-bit, dual-port memory. The Lucent devices come in 3.3 and 5V versions; the 3.3V models have 5V-tolerant I/O buffers.

  Altera aims to optimize memory performance and maintain design flexibility. Altera's Flex 10K architecture (Figure 4) forgoes a single block that can serve as memory or logic and instead combines two structures on a single chip—one optimized for logic and the other optimized for memory but still usable as logic. Those structures are the logic-array blocks (LABs), which include logic elements for random logic functions, and the embedded array blocks (EABs), which can implement either RAM in 2-kbit blocks or optimized logic functions, such as multipliers, ALUs, and DSP algorithms. If you do not use the EABs for memory, each EAB provides approximately 500 logic-gates' worth of logic.

  To connect blocks, Altera provides its FastTrack Interconnect, which comprises rows and columns of wire spanning the chip, thereby providing a routing mechanism that maintains predictable interconnect delays.

Dedicated memory blocks

  Using a dedicated-memory approach, Actel distributes 3238-bit blocks of dual-port RAM among the combinatorial and sequential logic modules that constitute the datapath circuitry throughout the company's 3200DX chips (Figure 5). Unlike the Xilinx and Lucent parts, the RAM blocks are dedicated to the RAM function. They offer 100-MHz performance but can implement random logic functions only when you use them as LUTs. In addition to RAM, combinatorial, and sequential modules, the Actel devices include address decoder modules that can decode a 35-bit address with array-to-pin delays of 12 nsec.

  Lattice Semiconductor combines general-purpose programmable logic with dedicated memory, as Actel does, but adds a dedicated register/counter/timer block (Figure 6). That block features eight banks of 16-bit functions; you can cascade the functions to 128 bits, and the block features independent read-from and write-to ability.

  As for memory, Lattice offers three devices, each optimized for FIFO memory or dual- or single-port RAM.

  "FIFOs are great for data-rate-matching buffers, where data is being written in at one speed and removed at another," says Kopec. "Dual-port RAMs are great for communication between two microprocessors or subsystems or where multiple intelligent bus masters are used, and single-port RAM is good for general-purpose, single-bus systems."

  Altera's Beachler calls all of these approaches to embedded PLDs "a logical progression."

  Says Xilinx's Vij, whose company introduced the RAM-capable XC4000 in 1991, "RAM in FPGAs is one of the most important functions you can have." The appearance of complex-PLD and other FPGA vendors in the embedded-memory market bears him out.

  Altera's Beachler elaborates on the evolution of embedded PLDs: "Before we introduced the embedded PLD in March 1995," he says, "we looked at what the mask-programmable gate-array vendors were doing. They were embedding microprocessor cores and memory and then surrounding that with regular gate-array gates. As field-programmable logic reached higher and higher densities, it made sense to embed memory. In fact, almost 50% of gate-array design starts now use memory to some degree, and the percentage gets higher at higher densities."

  Concludes Miller at Actel, "FPGAs with embedded memory are just the first of a new generation of more system-oriented building blocks," the precursors of what he calls system-programmable gate arrays.

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