Design Features November 21, 1996

Closed-loop flow control manages ATM channel bandwidth

David Copeland, Texas Instruments Inc

Using closed-loop flow control, you can keep the ATM data pipe wide as well as manage it efficiently. A primer in closed-loop flow control and the related ICs will help you implement this control scheme in your next ATM design.

  Closed-loop flow control allows switched networks to use the available bandwidth more efficiently, which in turn reduces congestion and data losses. This control method is an important development in networking, not only for ATM (asynchronous transfer mode) networks but also for more traditional LANs, such as Ethernet and token ring. ATM has served as a catalyst for the networking industry's movement to switching, and it has been a catalyst in the movement to virtual LANs. Now, ATM is playing the same role by introducing flow control.

  Early in 1996, the ATM Forum approved closed-loop flow control in the form of available-bit-rate (ABR) service in its Traffic Management 4.0 specification. A similar specification, I-371 Traffic Control and Congestion Control in B-ISDN, is currently under final ballot by the International Telecommunications Union (ITU).

  The newly defined ABR service category with closed-loop flow control adds several benefits to data communications on ATM networks. First, this control minimizes congestion and the resulting cell losses because the receiver can throttle the transmission rate when the network becomes overworked. Second, this control optimizes the network mix of bursty and steady-rate data because it enables fast ramp-up for data transmission when bandwidth is available. Third, ABR allows applications to take advantage of the statistical multiplexing capabilities of ATM to assign channels efficiently. Finally, ABR service extends the range of ATM utility, because applications such as LAN emulation, Multi-Protocol Over ATM (MPOA), RFC1577, and others can make use of the many possible connections to send their own frames.

  The ABR service category in the 4.0 specification provides the mechanism for networking OEMs to implement flow control successfully in their products. Now that the specifications are firm, manufacturers of ATM equipment are investigating ways to introduce flow control into their next-generation products, and silicon vendors are supplying a variety of ICs.

  Although all this activity represents an important step forward, it may be somewhat confusing if you haven't kept up with ATM technical developments. Simply put, closed-loop flow control is a form of traffic management with feedback that governs the rate of data flow between two points, thereby improving the efficiency of overall bandwidth utilization in a switched network. When ATM was originally introduced, the promised bandwidth of 155 Mbps seemed astronomical compared to 10 Mbps for Ethernet and 4 or 16 Mbps for token ring. But one of the ironclad laws of communications is that no matter how big the pipe, data soon fills it until it overflows.

  In the case of ATM networks, which can carry real-time voice and video, a particularly important design criterion is not to clog the pipe with large bursts of data that are not time-critical. Now that designers have successfully deployed ATM in backbones, network managers want to use ATM's huge bandwidth efficiently in a variety of applications that send different types of data.

  The ATM Forum specification defines five categories of traffic management services, including the newest ABR category version, as defined in Traffic Management 4.0. At the low end of quality and performance is the unscheduled-bit-rate (UBR) category, in which an ATM source simply sends data with no guarantee about transmission speed. Next is the constant-bit-rate (CBR) category, in which the source sends data at an unchanging speed. Still more sophisticated are two categories of variable-bit-rate (VBR) service for real-time and non-real-time data that allow the source to burst at peak cell rates.

Feedback changes transmission rate

  None of these service categories provides a feedback mechanism that allows the receiver to inform the source of how much bandwidth is available. However, the newly defined ABR category provides this mechanism in the form of resource-management (RM) cells or explicit flow-control indications in data cells, so that the receiver or network can throttle the source's transmission rate in response to changing network conditions. Before the system opens a transmission channel, the end systems agree on parameters that include a peak cell rate and a minimum cell rate. Because the minimum cell rate can equal 0, unused channels can remain open, allowing thousands of connections to establish themselves simultaneously. Figure 1 shows the ABR protocol in operation.

  Because of the speeds involved in ATM, hardware implementations of ABR at the source and destination are necessary. In general, designs are based on three types of ICs: traffic shapers, RISC coprocessors, and schedulers. The traffic shaper is low in cost but also low in connection support. The RISC coprocessor provides the highest performance but at a high cost. The scheduler provides the greatest design flexibility.

Traffic shapers are "leaky buckets"

  Some segmentation-and-reassembly (SAR) devices currently implement the traffic-shaping function. Traffic shapers buffer data by filling up quickly during bursts, then steadily feeding data out to the SAR at a lower rate. Because of the way traffic shapers operate, they are also known as "leaky buckets": the bucket fills from the top and leaks out the bottom. IC manufacturers can integrate traffic shapers with SARs, and some single-chip combinations exist. In the very near future, you will likely see traffic-shaper ICs with architectures that support ABR.

  Unfortunately, this approach has a drawback: integrated designs tend to implement only a handful of leaky buckets in a single device because of the complexity of the implementation. This approach is acceptable when several virtual channels use one leaky bucket. However, ABR requires scheduling for each virtual channel. Hence, ICs that implement this approach only support a handful of ABR connections. Because of the combination of low cost and low performance that leaky buckets offer, they are best suited for serving desktop ATM applications, particularly in networks running at 25 Mbps. For connection-intensive applications, such as file servers or LAN emulation in switch uplinks, leaky buckets are a poor choice.

RISC coprocessor has performance to spare

  In contrast, a RISC-coprocessor design has performance to spare for ABR scheduling and determining source and destination behavior. Unlike the traffic-shaper approach, which is limited by the number of connections it supports, the speed of the processor limits a RISC-based design. As a result, a high-performance RISC design can support a large number of bursty and steady-rate connections. The drawback to this approach is high cost, not only for the high-end RISC processor itself, but also for the substantial amount of external memory that stores programs and caches data, and for a bus interface among the devices. The combination of high performance and high cost makes the RISC-based solution appropriate for high-end applications, such as LAN emulation in ATM uplinks for Ethernet and token-ring switches. RISC designs are not suitable for cost-sensitive ATM applications, such as stackable switches and file servers.

Schedulers provide flexibility

  The most flexible alternative for designers is the scheduler, a device that performs ABR scheduling and determines source and destination behavior. Like the RISC approach, the scheduler is flexible and serves as a SAR coprocessor. However, unlike a general-purpose RISC, the scheduler integrates only the functions that it needs to perform its role as an ABR traffic cop for the SAR. As a result, a two-chip SAR-scheduler solution offers performance comparable to the RISC-based solution at a much lower cost. Because the scheduler can support a large number of ATM connections, it is suitable for ATM uplinks from stackable LAN switches. This approach is also appropriate for cost-sensitive applications such as file servers.

  Additionally, the scheduler is suitable for virtual source/virtual destination implementation in a switch. As Figure 2 shows, this implementation supports backward-compatibility by allowing a port on a switch to spoof or pretend to be an ABR destination, so that the switch can connect to equipment that does not support ABR.

  Figure 3 shows one design based on a two-chip scheduler/SAR combination. Functionally, the SAR implements high-performance segmentation and reassembly and is usually optimized for certain types of applications. The application-independent scheduler implements ABR source and destination parameters, parses and generates RM cells, and schedules cells for transmission.

  Figure 3 shows the two ICs, support memory, and the scheduler's interfaces. The coprocessor interface handles information passed from the SAR about cells sent and received, and information passed to the SAR about scheduling. The scheduler snoops the SAR's physical-layer interface to receive ABR control information, and it stores and retrieves ABR parameters for ABR connections through the memory interface. Figure 4 shows a LAN switch design that uses the SAR-scheduler approach for an ATM uplink.

  The advantage of a programmable scheduler is that you can use it to implement the preferred policies of the 4.0 specification and then easily modify the design to accommodate future developments. For example, the current Traffic Management 4.0 specification offers three system examples for implementing "use it or lose it" policies that autonomously reduce bandwidth for connections. Similarly, the parameter size of the variable CRM (a count of missing RM cells) is implementation-specific. Other features of ABR are not yet determined: the ITU specification provides optional fields in the RM cell for uses that are not yet clearly defined, and consortia and standards bodies have planned to incorporate other features in future specifications.

  The scheduler/SAR combination offers the potential for a large number of connections and allows for design customization and future modification. As a result, this type of design is well-suited for high-end applications, such as LAN emulation in ATM uplinks, and cost-sensitive applications, such as servers. Flexible approaches make it easier to implement ABR flow control in next-generation ATM products.  

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