Design Ideas February 3, 1997

EPLD configures wait-state generator

Wally Tjanaka, Philips Semiconductors, Sunnyvale, CA

Using a faster microcontroller or microprocessor in an existing application can boost the performance of a system. Unfortunately, interfacing the faster processor to the much slower existing peripheral ICs is a complex task. To overcome this problem, new processors, such as Philips XA, have an external wait-state-insertion capability. Given this wait-state feature, the tricky part is to generate the wait-state signal itself. In many cases, you can use one-shot ICs, such as the 74HCT221. Unfortunately, these ICs have a slow response time. This Design Idea shows how to build a wait-state generator with a fast response time (5 nsec, typically) using an EPLD. A benefit of using an EPLD is that you can integrate other glue logic, such as address decoding, into the EPLD.

  Figure 1 shows a typical scheme for generating a wait-state signal. Figure 1a shows the typical hardware configuration. In general, SIGNAL represents either the read or write signal of the processor. WAIT-STATE INPUT is the input where the wait-state signal enters the processor. Figure 1b shows the typical signal relationship in wait-state mode. Usually, the WAIT-STATE TRIGGER is a function of SIGNAL (SIGNAL TO STRETCH) and other signals, such as an address-decoding signal. WAIT-STATE TRIGGER triggers the wait-state generator to trigger WAIT-STATE SIGNAL. SIGNAL will be asserted as long as WAIT-STATE SIGNAL is asserted. When WAIT-STATE SIGNAL is deasserted, SIGNAL will be deasserted after some delay. Consequently, WAIT-STATE TRIGGER will be deasserted. This sequence is shown in Figure 1b as timing points 1 through 6.

  The wait-state generator uses a Philips PL22V10-10 EPLD. The logic circuit uses an asynchronous circuit. Listing 1 lists the logic-equation implementation, written in PLDShell Plus. The method implements all signals as active high. However, you can modify the logic to suit any need. Figure 2 shows the circuit configuration. Two input pins and four output pins implement the wait-state generator. TRIG is a positive edge-triggered input that triggers the circuit to start the wait signal. STOP is the input signal the circuit uses to deassert the wait signal. START is the output signal the circuit uses to start the wait-state signal sequence. WAIT is the wait-state signal.

  Y0 and Y1 are internal-state variables, which you should leave unconnected. An RC circuit provides the timing mechanism. When WAIT-STATE TRIGGER is asserted at TRIG, the circuit sets the START signal to logic 1 to drive the RC circuit. At the same time, the WAIT-STATE SIGNAL at WAIT sets to logic 1 (asserted). The RC circuit delays the input STOP from immediately seeing the high level. When the signal at STOP is high, the circuit sets START and WAIT to logic 0. At this time, diode D accelerates the discharge of capacitor C. Consequently, STOP sees a low signal when C fully discharges. When STOP is low, the circuit resets itself to be ready for the next trigger signal.

  You can use the expression t_PULSE=0.2744RC to approximate the wait-state signal's width. Note that if you use 22V10s from other manufacturers, this expression may be invalid, because the circuit uses the analog feature of a digital CMOS IC. This analog feature may differ among 22V10s if different processes are used to manufacture the IC. Figure 3 shows the waveforms that define the circuit's typical timing characteristics.

  The circuit's theoretical maximum response time (t_RESPONSE) is 10 nsec. t_RESPONSE is defined as the time delay between WAIT-STATE TRIGGER and WAIT-STATE SIGNAL. In practice, the typical response time is about 5 nsec. The hold time (t_HOLD) is defined as the time the WAIT-STATE TRIGGER must remain stable after the WAIT-STATE SIGNAL goes low; t_HOLD should be approximately 30 nsec or greater. If not, the WAIT-STATE SIGNAL oscillates only around the falling edge (not the whole signal). Depending on your applications, you may be able to violate t_HOLD and tolerate some oscillation around the falling edge of the WAIT-STATE SIGNAL.

  Figure 4 shows the reduced state table of the asynchronous circuit. Figure 4a shows the reduced state table before state-variable assignment. Figure 4b shows the reduced state table after assignment of the state variables. The logic equations are as follows:

Y0 = TRIG + /y1.y0./STOP
Y1 = y1.y0 + y1.TRIG + STOP.TRIG
WAIT = /y1.y0./STOP + /y1./STOP.TRIG
START = /y1.y0./STOP + /y1./STOP.TRIG

  The slash ("/") symbol is the NOT operator. The plus ("+") is the OR operator, and the dot (".") is the AND operator. Uppercase letters indicate next-state variables, for example Y1 and Y0. Current-state variables, for example y1 and y0, are indicated using lowercase letters. Note that, even though WAIT and START have the same equation, they are implemented on different pins to provide START with maximum current-driving capability. (DI #1986)

FIGURE 1	FIGURE 2
A typical wait-state generator (a) uses glue logic to produce a wait-state signal for a microprocessor. A typical wait-state timing sequence (b) consists of six discrete points in time.	An asynchronous circuit using a 22V10 EPLD implements a programmable wait-state generator.

FIGURE 3	FIGURE 4
The theoretical maximum response time of the wait-state generator in Figure 2 is 10 nsec; in practice, it's typically about 5 nsec.	The reduced state tables of the wait-state generator in Figure 2 show the states before (a) and after (b) state-variable assignment.

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