EDN Access

 

April 24, 1997


Single chip brings built-in test to analog designs

Vincent J Spataro, GEC Marconi Hazeltine Corp

Traditional built-in test techniques for analog systems require considerable board space and I/O lines. You can now add those techniques with a single IC. The software listings in this article are available on EDN's Web site, www.ednmag.com, in the registered-user section, Listings adc0858.cpp and pport.cpp.

As electronic systems be-come increasingly complex, the need to provide fast, accurate, low-cost fault isolation becomes critical. Designers need to include built-in-test (BIT) circuitry to ease the burden on the repair technician and reduce the product's mean time to repair (MTTR). BIT circuitry can isolate circuit faults down to functional groups of parts or sometimes to a single component. In the digital domain, you can, to a large degree, perform BIT in software. For analog designs, unfortunately, the problem of providing BIT is much more complex.

Analog BIT traditionally requires substantial circuitry and a large number of I/O lines to obtain useful data. Typically, analog signals monitored for BIT applications lie within narrow windows when the circuit operates normally. Such signals need two comparators, several passive components, and two I/O lines for proper monitoring. This complexity results in high cost and a large allocation of circuit-board area for BIT functions. To reduce circuit complexity and the number of I/O lines necessary, designers often logic-OR BIT information together. A so-called "summary BIT" results, along with the loss of useful information.

If a circuit designer put together a list of features for the ideal analog BIT, it might include

  • a dedicated channel for each analog signal to be monitored,
  • programmable upper and lower test limits,
  • the ability to determine the actual voltage value at the
    failed analog test point,
  • serial output to minimize the number of data lines necessary,
  • compatibility with a microcontroller or PC,
  • low cost, and
  • a small footprint.

These goals are difficult to meet using traditional analog-BIT methods. The complexity that the circuit requires to implement all the desired functions conflicts with the need for low cost and small size. Designers usually have to compromise, including as much functionality as can be supported within the limits of board area and monetary constraints.

Chip helps analog BIT

Surprisingly, however, one commercially available chip meets all these requirements: the National Semiconductor (Santa Clara, CA) ADC0858. The ADC0858 is a 20-pin, 8-bit analog data-acquisition and -monitoring system. (See box, "The ADC0858: a closer look") Although not specifically designed for BIT, the ADC0858 can be successful in that application. It can monitor eight separate analog inputs and determine whether these inputs are inside or outside user-preprogrammed limits. The ADC0858 requires few external components and only five I/O lines to perform upper and lower limit comparisons on its eight channels. Compare this number with at least 16 I/O lines and a good deal of associated circuitry to implement this function using a traditional comparator approach.

The ADC0858 needs a host processor for setup and control, but monitoring takes place independently of the host processor or PC. This "watchdog" mode of operation frees the host processor from the need to continually interrogate BIT. When the ADC0858 detects that a signal is outside its limits, the device flags the host processor. The processor can then interrogate the chip to determine which signals are outside their respective windows. The processor can also read the voltage at any channel.

You can use several approaches to configure a system using the ADC0858 to provide BIT. In systems that employ a microcontroller, the controller programs the ADC0858 at start-up and then waits for it to generate an interrupt. BIT is continuous and "online."

Systems without a microcontroller can employ one summary BIT to flag a bad circuit card. When the repair technician removes the board for repair, he can use a PC to interrogate the ADC0858 and determine the cause of failure. Even circuit boards that connect to a host microcontroller in the assembled unit can connect to a PC at the repair depot to provide additional testing versatility.

To successfully implement analog BIT, it is important to understand the ADC0858's limitations. For example, a principal source of error in the ADC0858 is the 3-µA leakage current of its multiplexer input line. For a 1-kilohms input resistor, this leakage results in a 3-mV voltage drop, which reduces the measured signal voltage. If you use capacitive filtering at the input pins of the A/D converter, you should keep the source impedance below 1 kilohms.

Another error results from the A/D converter's sampling function. At the rising and falling oscillator clock edges, spikes of current enter the "+" input line and exit the "­" input line. With low input-signal source impedances, these spikes quickly decay and settle out before the A/D conversion begins. For high impedances, however, the transients may not completely settle and may affect the desired signal.

You should cautiously undertake monitoring signals with impedances greater than 1 kilohms. Under typical operating conditions, the ADC0858's total unadjusted error is approximately ±0.2 LSB for source impedances less than 2 kilohms. If you can sacrifice accuracy, you may be able to tolerate a higher impedance. If you must accurately monitor a high-impedance point, consider buffering the point with a voltage follower.

Applications that monitor low-impedance points are thus less likely to introduce measurement errors in the ADC0858. Some good applications for the chip include monitoring input and output supply voltages; active- or passive-filter, comparator, and operational-amplifier outputs; voltage references; oscillator outputs (with appropriate filtering); and battery voltages. Points such as high-impedance operational-amplifier inputs, RF circuits, inputs to oscillators and VCOs, and noisy low-level signals are poor monitoring candidates.

Another concern with using the ADC0858 in BIT is that the input voltages to be monitored may exceed the device's safe input-signal range (VCC to GND). For example, the chip may monitor the output of an operational amplifier that has a voltage swing between the power rails of ±15V. During normal operating conditions, this output may sit between the positive and negative rails and may not pose a problem. However, during start-up or shutdown, the output may swing to either rail, damaging the ADC0858.

To prevent such damage, you need to protect the ADC0858's input lines. You would typically use two clamp diodes, one that clamps excessive positive voltages to VCC and another that clamps negative voltage swings to ground. Reference 1 describes a circuit that protects the ADC0858.

Consider clock timing

Another design aspect that requires care is the ADC0858's digital-signal-timing requirements. Signals such as CS, CLK, and DI are likely to run at high frequency if they originate from a microcontroller. If these signals originate from a PC, they are likely to be quite slow because they are software-controlled. Although the ADC0858 can support slow data, the rising and falling edges must be clean. A Schmitt trigger buffer at these inputs guarantees clean waveform edges.

When designing the ADC0858 into a BIT circuit, it is important to separate analog and digital grounds. You also need to decouple VCC to digital ground and VREF to analog ground. A 10-µF solid tantalum capacitor in parallel with a 0.1-µF ceramic capacitor work well at each location. To minimize the interaction of the BIT circuitry with the circuit card under test, choose only low-impedance points to monitor, employ proper grounding and decoupling techniques, keep sensitive circuitry away from the ADC0858's 1-MHz clock, and keep all runs as short as possible to reduce stray signal pickup.

Circuit aids software development

A simple development circuit allows you to use the ADC0858 in a variety of BIT applications (Figure 1). During software development, eight potentiometers provide input signals to ADC0858 channels CH0 to CH7. A 0.1-µF capacitor at each input filters out noise to prevent false tripping. C6 and R3 set the internal oscillator's timing to 1 MHz. A transistor drives an LED, which lights when the ADC0858 generates an interrupt in its watchdog operating mode.

In the actual application, fixed resistor dividers replace the development circuit's potentiometers. The only other components that are necessary on the circuit card under test are the data-acquisition chip itself, RC network R3 and C6, and the analog and digital decoupling capacitors.

The development circuit is designed to connect to the parallel port of an IBM-compatible PC for setup and control. (See box, "Using the PC parallel port.") IC3 and IC4 are Schmitt trigger inverters that buffer the PC parallel port and also square up the input pulses, which could be relatively slow. The one-shot, IC2, produces a pulse that changes the ADC0858's operating mode. Although the PC could generate this pulse, the pulse has specific timing requirements and would require careful control by the PC. Using a one-shot makes the pulse independent of any PC clock-speed variations.

Using a PC eases programming of the ADC0858. You can program in Basic, Pascal, or C. The program adc0858.cpp is written in Borland Turbo C++, V3.0 (Listing 1, pg 138). To remain ANSI C-compatible, the program uses no C++ features. It allows the user to program eight analog channels (CH0 to CH7) with upper and lower BIT-window limits. After entering the watchdog mode, the ADC0858 flags the PC when a signal crosses its limit.

Figure 2 illustrates the main program steps. After initialization, the program writes BIT limits into the ADC0858 and then reads them back to confirm that the limits are correct. The program then sets the ADC0858 in watchdog mode and waits for an interrupt. When an interrupt occurs, the program reads tag and status registers. The program normalizes the status register, bit-rotating the status register by the contents of the tag register. This rotation lines up the least significant bit of the status register with CH0 and the most significant bit with CH7. The program displays results on the PC's monitor.

BIT checks power supply

One use of the development circuit is to perform analog BIT on a switch-mode power supply (SMPS). Figure 3 shows how you accomplish this analog BIT. The ADC0858 development-circuit input channels (CH0 to CH7) monitor selected test points in the SMPS circuit. You use a PC or microcontroller to program the ADC0858 and to send data to and from the device. The buffers on the development board safely isolate the PC or microcontroller from other circuitry, and, although they are helpful during development, the buffers are unnecessary in the final onboard circuit application where space may be at a premium.

Figure 4 shows the circuit under test in greater detail. It is a typical flyback-topology SMPS with two output voltages. VOUT1 is the main regulated output voltage, and VOUT2 is a secondary voltage derived from a linear post regulator. A PWM IC controls the single-transistor switching circuit. A start-up circuit provides power to the PWM IC until the switching circuit becomes self-sustaining. Then, the IC's power comes from the feedback winding on the power transformer.

You should choose BIT-monitoring points that partition the circuit into functional groups. The input line and all output voltages are obvious choices. You can use additional test points to isolate the input-filter circuitry. You should also monitor the control circuit to isolate its function from the power section. Circuit reference voltages and feedback points are also good candidates to monitor. All signals should be low-impedance compared with the input impedance of the ADC0858.

The signals monitored in this example are

  • CH0--dc input line,
  • CH1--filtered dc input line,
  • CH2--VOUT1,
  • CH3--input to the linear regulator,
  • CH4--VOUT2,
  • CH5--PWM IC output,
  • CH6--PWM IC reference, and
  • CH7--feedback winding (VCC to PWM).

You can use the development circuit to directly monitor each of the eight test points listed by replacing the potentiometers with fixed resistor dividers to scale each signal to an appropriate level. You also need to program the ADC0858's limit windows appropriately.

Note that CH5 employs an RC circuit as an integrator. The integrator converts the PWM's rectangular pulse into a filtered dc level that the ADC0858 can monitor. The RC time constant chosen produces a dc level with small ripple at the PWM's operating frequency. The BIT window limits should correspond to the dc levels that represent the minimum and maximum PWM duty cycle expected in normal operation.

Choose test points for fault isolation

To use this circuit for fault isolation, you need to evaluate the various possible combinations of test-point failures. Consider, for example, a case in which all channels except CH4 register within limits. The error on CH4 would lead you to suspect the linear regulator. If say, CH0, CH1, CH5, and CH6 are all within limits, but CH2, CH3, CH4, and CH7 are out of tolerance, then the switching transistor is suspect. If only CH0 is within tolerance, the input filter is probably the culprit. Thus, if you have carefully chosen the test points, the BIT can quickly point a repair technician to the faulty components.

With ICs such as the ADC0858, low-cost but effective analog BIT is possible for many circuit applications. Both connecting to and programming the ADC0858 are relatively simple tasks, using either a microcontroller or a host PC. The keys to successful analog BIT then become proper selection of test points and control of test-point electrical characteristics. Cost and footprint are no longer issues.


References

  1. National Semiconductor Data Acquisition Databook, National Semiconductor Inc, Santa Clara, CA, 1995, pg 1-5 to 1-36.
  2. Johnson, JH, Build Your Own Low Cost Data Acquisition and Display Devices, TAB Book, Division of McGraw-Hill, New York, 1994, pg 154 to 196.
  3. Bergsman, P, Controlling the World with Your PC, HighText Publications Inc, San Diego, CA, 1994.

The ADC0858: a closer look

The National Semiconductor ADC0858 (Figure A) is a single-chip data-acquisition system that can serve the needs of analog built-in test (BIT). The chip includes RAM, an 8-to-1 multiplexer, a DAC, an oscillator, and control logic. Each of the eight input channels connects to the 8-to-1 multiplexer, which selects one channel for connection to the ADC. The ADC has an 8-bit resolution with a total error of ±1/2 LSB or ±1 LSB, depending on the version of the device. An external reference voltage reference determines the A/D converter's range. Analog conversion takes place in 18 µsec per channel.

The device requires two clocks for operation. A clock signal for the A/D conversion comes from the chip's internal oscillator, set by an external RC network. This internal clock typically operates at 1 MHz. An external clock, derived from the host processor, clocks serial data into or out of the device through the DI and DO lines. This clock can be quite slow, if desired, as long as the rising and falling edges are squared up by using a Schmitt trigger.

ADC0858 analog-input ports can operate as single-ended, pseudodifferential, or true differential channels. In the single-ended mode, the A/D converter uses COM, which is at analog ground, as its reference. In the pseudodifferential mode, individual outputs also use COM as their reference, but COM may be at a voltage offset from analog ground. The true differential mode looks at the relative voltage difference between pairs of inputs. The ADC0858 allows you to individually set the mode of each channel.

RAM holds window limits

The ADC0858 RAM functions as a window comparator by storing both upper and lower voltage limits corresponding to each analog-input channel. The limit comparison takes 2 µsec/limit. Limit data not only can be written into RAM, but also can be read back. This important aid to testability allows BIT software to verify test limits.

The ADC0858 makes the following modes available to the designer:

  • watchdog,
  • write one limit to RAM,
  • write all limits to RAM,
  • read one limit from RAM,
  • read all limits from RAM,
  • initiate one A/D conversion, and
  • initiate auto A/D conversion.

The ability to operate in the watchdog mode makes the device particularly useful for BIT. In the watchdog mode, the device successively compares each input signal with the associated limit values in RAM. This behavior continues without action from the host processor. Only if a signal violates its limits does the host get involved.

If an input signal exceeds either of its limits, the device stores a 1 in the most significant bit of the status register. The device then updates a tag register to hold an address that indicates which channel crossed a limit and whether the limit was an upper or lower limit. After detecting the first limit crossing, the chip cycles once through the remaining channels and compares them to their respective limits. For every other limit violation, the device places a 1 in the appropriate location in the status register. After cycling through all inputs, the ADC0858 sets its INT pin low, providing an interrupt to the host processor.

After receiving an interrupt, the processor has several options. It can bring CS low and synchronously shift out the serial data to determine which channel crossed which limit. The processor can also initiate an A/D conversion on any or all channels to read the actual voltage at any test point. Thus, the ADC0858 can both monitor analog signals for errors and provide an avenue for examining the error condition.

The ADC0858 can operate from one 5V supply and an external reference voltage to set the A/D converter's range. The ADC0858 is available in a compact 20-pin PLCC or 20-pin ceramic DIP. For military users, /883 screening is also available. The ADC0858 costs less than $10 in small quantities.

Using the PC parallel port

The IBM PC's parallel port can do more than drive printers. It can also be a useful tool for control applications. What you need to know is how the port handles signals.

You access the PC's parallel port by writing to the three memory addresses that make up the port. The data-output register (BASE) address holds the port's output data. Typically, BASE is at address 378h for LPT1 and 278h for LPT2. On some machines, however, the LPT1 port may be at 3BCh. You can run the PC's setup program to see what location your machine is using. The next address, BASE+1 (input-status register), looks at the input-status lines. You can use these lines to bring data into the PC. At location BASE+2 (output-control register) are four output-control lines.

The parallel port on the PC uses a standard DB-25 connector, with pins 18 to 25 tied to ground. You should use a standard serial cable to connect the PC to your circuit. Do not try to use a modem cable; not all of the cable's lines are connected.

Table A, the PC port-address map, shows the names, pin assignments, and bit locations of each signal. Notice that for the input-status register and output-control registers, not all bit locations have definitions. When the PC reads the input-status register, the unused bits may contain superfluous data that can produce unpredictable results. You can solve this problem by logic ANDing the input-status word's 3 least significant bits with zero to force the 3 bits to always be zero.

Table A--I/O assignments on the PC parallel port

Bit number 7 6 5 4 3 2 1 0
Base: data output Data Data Data Data Data Data Data Data
DB-25 pin number 9 8 7 6 5 4 3 2
Base+1: input status Busy Ack Paper
end
Select Error      
DB-25 pin number 11 10 12 13 15      
Base+2: output control         Select
input
Initialize Auto-
feed
Strobe
DB-25 pin number         17 16 14 1

BASE uses positive logic. BASE+1 treats all input signals except BUSY as active high. BUSY is hard-wired inside the PC to be active-low. The PC thus interprets signals on this line as inverted logic levels. You can, however, ignore the negation bars for the acknowledge and error input lines. These names are merely conventions specific to printer-control logic. Both these signals look active-high to the PC. For BASE+2, the negation bar above three of the outputs indicates that they are active-low signals.

Figure B shows a useful circuit for developing parallel-port applications. You can use it to test and debug your software before final hardware is ready. The circuit uses LEDs to show the status of each parallel-port I/O line. Sending a logic high out on any bit lights the corresponding LED. Inverting buffers provide the correct polarity to drive LEDs. The buffers also isolate the circuitry from the PC.

The BASE+1 address looks at the logic state of five spst switches. Remember, though, that the BUSY input is inverted. Similarly, at location BASE+2, a logic high lights the INITIALIZE LED, but a logic low is necessary to light the three remaining LEDs as the PC inverts the logic on these lines.

Circuit construction uses a Radio Shack Experimenter's plug-in card (Stock #276-1598), which provides for a pc-board-mounted DB-25 connector. This DB-25 simplifies connection to the PC parallel port. A sample program, pport.cpp, tests both the output LEDs and the input switches (Listing A). The program is commented and should be simple to follow.


Author's biography

Vincent J Spataro is a principal engineer with GEC Marconi Hazeltine Corp (Wayne, NJ), where he has worked for 12 years designing high-reliability analog and power-supply circuits. He holds a bachelor's degree in physics from Fairleigh Dickinson University (Teaneck, NJ) and a master's degree in engineering physics from Stevens Institute of Technology (Hoboken, NJ).


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