December 4, 1997

Multiplexers convert deep
FIFO buffer to bidirectional

Kevin Kelley, Telephonics Corp, Farmingdale, NY

Interfaces to digital data recorders often require deep FIFO buffers to match the system's data rate to the recorder rate. Sometimes, a second set of FIFO buffers in the opposite direction handles playback data. Doubling the FIFO-buffer size in this manner has obvious disadvantages in cost, power consumption, and board area. Inasmuch as you need only one data-flow direction at a time, you can use one FIFO buffer (Figure 1). The circuit converts a 32k×16 SuperSync FIFO design to bidirectional (half-duplex) using QuickSwitch QS3390 16-to-8 multiplexer/demultiplexer ICs. This implementation has the following advantages over the traditional tristate-multiplex/demultiplex approach:

• Near-zero propagation delays through the multiplexers produce minimal impact on high-speed data-flow timing through the FIFO buffer in either direction;
• This implementation requires fewer ICs: four QS3390s vs eight octal tristate buffer ICs (note that QS3390s are 28-pin devices and octal buffers are 20-pin ICs); and
• It consumes less power than a design using conventional buffers, because activity on the A, B, and C pins of the multiplexers does not contribute to the power dissipation of the devices, which consume 9 mA maximum each.

In this circuit, the Record_L and Playback_L signals are mutually exclusive; at any time, a low state determines the direction of data. When Record_L is low, it selects the A port to write into the FIFO buffer along with the A-port clock; the B port receives the FIFO data along with the B-port clock. When Playback_L is low (Record_L is high), the B port writes to the FIFO buffer and the A port receives the data. The QS3383 switches the FIFO read and write clocks and enables the FIFO buffer to match the ports. To avoid bus contention, you should tristate the devices driving the A and B ports during direction switching. (DI #2105)

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