December 4, 1997

Software speeds 8051 RS-232C receiver

Jerzy Chrzaszcz, Warsaw University of Technology, Poland

This method allows for receiving data from a half-duplex, 9600-bps or faster serial link in an 8051-based system without using a hardware UART. The method's goal is to minimize performance degradation that software-service routines incur. Bit-cell time for 9600-bps transmission with 8 data bits, no parity, and 1 stop bit (8N1 format) is approximately 104 µsec. This rate translates into 96 processor cycles if you use an 11.0592-MHz crystal. Thus, 960 processor cycles are available during byte-frame reception.

The proposed solution is based on Reference 1. The technique uses external interrupt INT1 as a data-receive line. Timer T0 generates the sampling timebase using mode 2 (8-bit autoreload) (Figure 1). In idle state, the timer remains stopped, and the external interrupt enables. The start of an incoming data frame produces an INT1 request. The interrupt-service routine loads, starts the timer, and disables INT1. Upon initiation of the process, the first timer interrupt verifies the start bit, so the initial delay is approximately half the bit-cell time. Then, the system samples 8 data bits and, during the service of the tenth timer interrupt, validates the stop bit. The timer stops, and INT1 re-enables to ready the system for the next byte (Figure 1a).

A receive sequence consumes 264 processor cycles. The time between "data ready" and clearing the received byte after identifying the next start bit is only approximately 90 cycles for back-to-back transmission. If the main program cannot accept data within that time, an overrun error arises. The modified code in Listing 1 is the receive-related part of an 80C51 service routine that trades framing-error detection for execution speed. Click here to download this listing DI-SIG, #2125.

The technique does not verify start and stop bits and samples only data bits on timer ticks. The external interrupt is edge-sensitive to avoid false triggering when the last data bit is 0. Consequently, the bit-receive procedure is simple and fast. The data-ready condition becomes flagged after reception of the last data bit, and, because the sampling point resides at the beginning of the bit cell, the flagging occurs approximately 1.5 bit cells earlier than it does in the original code (Figure 1b). Such timing increases the chance to use the data, but just to be sure, the method copies the byte to another memory location. This technique mimics double-buffer operation of a hardware UART and gives the processor an additional 1.04 msec when it receives the next byte. The reworked receive sequence lasts 179 cycles, representing an approximate 30% speed improvement. (DI #2125)

Reference

1. Application Note AN423, "Software driven serial communication routines for the 83C751 and 83C752," Philips Semiconductors.

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