Practical Chip Design

May 15 2008 6:03PM | Permalink | Email this | Comments (0) |
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If there's a common thread that can string together many of the product announcements in these frenetic weeks before DAC this year, it is performance. So far at least, there doesn't appear to be a lot going on in terms of new kinds of tools or new ways of approaching the more-than-documented problems of advanced CMOS design. Rather, tool vendors seem to be circling back to make existing tools fast and efficient enough to handle today's chip designs in more than a fragmentary fashion.

We've previously discussed moves to port the core algorithms of some tools to graphics processors, moves to multi-thread existing engines to spread them across multiple cores, and just plain efforts to find better algorithms for core functions. (See, for instance, here.) There is a new-found interest, for example, in importing sparse-matrix solvers from other applications such as imaging, geological and structural analysis.

All of these efforts are driven by the complexity ramp. Not only are chips getting more complex—only an issue for tools that must handle an entire chip as a flat data set—but individual blocks are getting more complex functionally. In addition, underlying device models for analog and RF simulations are getting more complex, and as frequencies increase, the meshes that include all the potentially significant parasitics are growing like a healthy fungus in a warm pudding. And many functions require verification that skips back and forth between the analog and digital, and between abstract and gate-level, domains, putting further pressure on both performance and the size of data sets that must be exchanged.

Yet another example of the search for performance came yesterday, when Jasper Design Automation announced a new version of its formal verification tool. The claim is a three-fold increase in circuit capacity, based on a factor of two improvement in memory utilization; and a factor of ten better engine performance. Further, and also in an attempt to adapt to what design teams are actually doing these days, the new Jasper tool is said to automatically extract information on gated clocks and to process gated-clock logic correctly without an elaborate song and dance by the user. Increases in user interactivity, including the ability to input a constraint on the command line instead of having to edit and recompile the whole model, add to throughput.

The ability to handle larger chunks of logic—while still far from claims of full-chip formal verification—will be welcome. The interactivity will be welcome also, as innovative design teams begin to extract formal verification from the verification world and use it as an exploration tool at the architectural level.

Related entries in: EDA | SOC (System on a chip) |