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The drive for SSDs: What’s holding back NAND flash?

Hagop Nazarian and Sylvain Dubois, Crossbar -November 26, 2013

In order to maintain acceptable performance characteristics at the user-level, storage systems designers for solid state drives (SSDs) have had to develop complex architectures and algorithms to work around the inherent limitations of NAND Flash. These workarounds have enabled fast and reliable memory solutions that have been successfully fueling storage systems for decades, but not for long. Here’s why.

Aside from being counterintuitive to the industry’s trend toward smaller and simpler technology, the complex system of workarounds has impacted overall performance and cost, while also causing major system bottlenecks, promising to only worsen as technology nodes continue to scale down

For example, when scaling below 25nm, NAND Flash has suffered such severe endurance and reliability degradation that its go-to workarounds now offer little help (Figure 1). Such performance measures have prompted an industry-wide race to develop a more robust non-volatile memory (NVM) solution to meet the capacity, performance, power and reliability requirements of next-generation electronic devices by simplifying the way memory works.

So, what’s holding back NAND Flash? Design constraints. Inherent design constraints. This article will discuss the challenges NAND Flash is facing as manufacturers attempt to scale down, specifically in solid state drives, as well as cover new, emerging memory technologies that will change the landscape of the NVM market.


Figure 1: NAND Endurance and Bit Error Rate (BER) Trends — As technology nodes decrease, NAND endurance cycles decrease and BER increases. Endurance measures how many cycles a memory cell can endure before becoming so error prone that it cannot be used. BER measures the rate of bit errors per memory array.


NAND Flash Design Constraints
In the most recently developed Flash-based SSDs, memory accesses are managed by a high-end memory controller chip connected to DRAM buffers and multiple raw NAND Flash components. Whereas most tech-savvy individuals are aware of NAND Flash technology’s limitations, a deeper look into the workarounds in place illustrate just how they impact SSDs and the overall system. These characteristics are summarized in Table 1.


Table 1. Summary of NAND Characteristics and Storage System related workarounds.


Block Erasure
NAND Flash technology can only erase blocks and can only program pages. Its inability to revise a fully programmed block at any granularity (byte, page or block), without erasing the entire block, is a design constraint that increases overall complexity with the following workarounds: data duplication, logical-to-physical mapping tables (L2P), buffering and garbage collection.

Data Duplication: For revisions of data, the NAND system controller must first read the data into a temporary memory location (like DRAM), then merge the read data with the revised data when required and finally rewrite the modified data to a new page (Figure 2).

L2P Mapping: Consequently, the controller must update and maintain L2P mapping tables every time this process is performed. L2P holds the original and revised data locations, directing the host so it can access and perform data management processes. The greater the capacity of the storage device, the larger these tables need to be. As such, most controllers must use external DRAM to maintain these larger tables.

Garbage Collection: The pages with obsolete revisions, also called stale data, cannot be erased or overwritten; instead, they are freed up by yet another controller-initiated workaround referred to as garbage collection. Figure 2 demonstrates the data revision process followed by the garbage collection process.


Figure 2. Garbage Collection Process – Twenty-four page writes occur to rewrite eight pages, which means Write Amplification (WA) equals three, triple the ideal measure of efficiency.

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