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Xilinx and OIF show 100G connectivity at ECOC, using CFP2 designs from Finisar

-September 30, 2013

In another era, fiber interfaces demonstrated by FPGA vendors at the European Conference on Optical Communications (ECOC) were a big deal. In the late 1990s, the appropriate physical-layer fiber for 10G Ethernet and Sonet was considered critical, and shows like ECOC and Optical Fibers in Communications (OFC) were must-attend affairs.  Then the optical and Internet recession of 2001 hit.

In the succeeding decade, Sonet all but vanished, to be replaced by the Optical Transport Network.  Optical OEMs fell by the wayside. Ethernet at 10 Gbits/sec experienced a slow rollout, which meant 40G and 100G Ethernet remained laboratory curiosities. And the OFC and ECOC shows lost a lot of luster, despite the service-provider and enterprise die-hards who still wanted to see new optical activity at switch and component levels.

The Optical Internetworking Forum, which absorbed Network Processing Forum seven years ago, never gave up the faith.  It pioneered many physical-interface and packet standards that were critical for the continued development of the all-packet optical network.

Xilinx and OIF came together at the recent ECOC to demonstrate a working 100G OTN link, using four 25-Gbit channels carried by a CFP2 module designed by Finisar Inc. Many vendors have worked with 100G links using the original ten-channel CFP, but a four-channel CFP2 may prove optimal, with a reasonable power budget.

Xilinx's Virtex-7 H580T FPGA uses GTZ transceivers operating at 28.05 Gbits/sec (25G plus overhead), linking to a Finisar module running at 27.95 Gbits/sec per channel. The interoperability demo shows the compliance with OIF's CEI-28G-VSR standard, at both physical and data-link layers.
This is hardly the end of the line for Xilinx.  The company revealed, at the time of its 3D process technology announcement two years ago, that it was working on a MAC for 400G Ethernet operation. Two years later, there are few system or board-level players even experimenting with 400G Ethernet yet.

Xilinx, and OIF by association, consequently finds itself in a position similar to Altera Corp with its work with on-chip optical subassemblies. The idea of placing a TOSA or ROSA inside an FPGA package could be revolutionary – if customers had the guts to design that way.

Links operating at 40G and 100G for both Ethernet and OTN are now commonplace. Markets may ramp slowly, the way they did for 10G Ethernet, but many data centers need this speed today.  It's too bad more designers aren't paying close attention to the OIF work at the optical trade shows.  Sure there are tough decisions to be made between four channels of 25G and ten channels of 10G to implement 100G links, but this should imply a market of system diversity, not one of OEM inaction.

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